AUTONOMOUS ROBOT FOLLOWING PREDEFINED PATH USING VHDL CODING - PART IV
In this final part we will discuss about the VHDL coding and the software used for the same.
LOGIC DISCRIPTION
1. An entity named vlsi_robot is declared with its input and output ports. Its input is clock (clk) and outputs are display (d), output (o), and select signal (s).
2. D is the bits for 7 segment display and select signal is 2 bit no. which is controlling the 7 segment display through latches.
3. Output bit o which is 4 bit data is going to the JP5 header and through which goes to the driver circuit.
4. In the architecture body, a intermediate variable q which counts the clocks, is declared.
5. When positive edge of clock occurs, the value of q is compared and according to these values, robot is made to move in forward and left direction.
6. After each comparison q is increased by 1.
7. Output ports 'o' and'd' are assigned the values according to 'q'.
8. When q is equal to 0000 or 0001 or 0010 or 0011 or 0100 or 0101 then output o is 0011 and display d is 0001110 (FF). When q is equal to 0110 or 0111 or 1000 then output o is 0101 and d is 0001000 (RR). S is selected "11".
9. When q is equal to 1001 then q resets to 0000 and the robot again retraces its previous path.
SOFTWARE USED: Quartus II Version 8.0
New Features, Enhancements, and Device Support:
"Quartus II software's incremental compilation feature offers users productivity advantage, capable of delivering up to a 70 percent compile time reduction compared to a standard compilation. Assisting designers in maximizing the full benefits that incremental compilation provides, Quartus II software version 8.0 features a new design partition planner. During the process of creating incremental compilation design partitions, an interactive graphical user interface (GUI) provides real-time feedback, such as logic resource usage and inter-partition timing paths, enabling designers to explore and quickly determine the most effective partition scheme".
Additional Enhancements to Quartus II Version 8.0
- New tasks window: Provides an interactive design flow console that guides users through the FPGA design: Offers support for incremental compilation including JTAG and SPI interfaces.
- Enhanced FPGA I/O planning: Accelerates board development with added pin-swapping capabilities in the Pin Planner.
- Mega Core Library: Integrated in Quartus II software, making it easier for users to access Altera's portfolio.
DOWNLOADING THE PROGRAM
The following steps are used for downloading the program in the CPLD kit-
The following steps are used for downloading the program in the CPLD kit-
1. In the new project wizard, the specifications about the CPLD kit are entered.
2. Then in the new project wizard, new VHDL design is selected. It will open a new window in which program will be written.
3. After writing the program the program is compiled in processing menu by selecting "start compilations".
4. If the program is correct, the waveforms are made by using vector waveform.
5. Then by using node finder, all the inputs and outputs are listed and then inputs are given user defined values.
6. After this step simulation is performed by using simulation tool in which functional type of simulation is selected and simulation function is generated.
7. Now the simulation is started by clicking the start icon. If simulation is successful, it will give the output waveforms according the input values.
8. After this step, pins used in the CPLD kit are assigned to the input and output variables. This step is done by using assignment editor in which device and pin option is selected.
9. The pin configuration is explained in the data sheet.
VHDL CODE:
Library ieee; -- to use the library ieee consist
-- Of various packages
Use ieee.std_logic_1164.all; -- to use all the names declared
Use ieee.std_logic_unsigned.all; --in packages
Entity vlsi_robot is -- declaration of the entity name
-- declaration of input and output ports of entity
Port (clk : in std_logic;
d: out std_logic_vector( 6 downto 0);
s: out std_logic_vector(1 downto 0);
o: out std_logic_vector (3 downto 0) ) ;
end vlsi_robot; -- end of the entity
Architecture robot of vlsi_robot is -- declaration of architecture
Begin -- start of architecture statement
process (clk) -- sensitive list
Variable q: std_logic_vector(3 downto 0):= "0000"; -- declaration of Intermediate variable
Begin
if clk'event and clk='1' then -- condition for clk
if q= "1001" then -- to reset the q
q:= "0000";
end if; -- end of if statement
if q= "0000"or q= "0001" or q= "0010" -- condition on q for
or q= "0011" or q= "0100" -- forward movement
or q= "0101" then
s<= "11"; -- outputs for indicating
d<= "0001110"; -- forward motion
o<= "0011";
end if; -- end of if statement
if q= "0110" or q= "0111" -- condition on q
or q= "1000" then -- for left motion
s<= "11"; -- corresponding outputs for
d<= "0001000"; -- left movement
o<= "0101";
end if; -- end of if statement
q:= q +1; --increment of q
end if; -- end of first if statement
end process; -- end of sensitive list
end robot; -- end of architecture
Furthur Readings:
Project Author: Deepika Daluka
Composed By: Aditya Sharma
.bmp)
1 comment:
Is there a video so we can see what happen.. and I have misunderstanding of the ports s and o.
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